One technique for improving performance of a software system is to implement selected sections as hardware accelerators. Those sections of the system that exhibit high computational complexity and consume large portions of total runtime may be suitable candidates for implementing as hardware accelerators. The hardware accelerators could be application specific integrated circuits (ASICs), graphics processing units (GPUs), or circuitry running on field programmable gate arrays (FPGAs), for example. A common approach employed by software designers in creating a hardware accelerator is to use a high-level synthesis (HLS) tool to convert the original high-level language (HLL) specification of the identified section into an equivalent register transfer level (RTL) or other hardware description language (HDL) specification of the circuit.
Although the generated RTL specification may be functionally identical to the HLL specification, the software designer may need to debug the implemented circuit in the course of system development. Issues involving timing, concurrency and race conditions may have been masked when developing the HLL specification and can surface during hardware testing. Also, differences in software and hardware library implementations, incorrect translation, or differences in memory access can create implementation problems.
Debugging the circuit implementation in FPGA hardware can be facilitated by instrumenting the hardware design. Before synthesizing the circuit design, the designer can specify additional debug circuitry (integrated logic analyzers) to monitor individual signals. However, in order to specify the debug circuitry, the designer must know the internal, low level signals to trace and the triggers to set in order to generate a waveform. The designer may find that multiple synthesis iterations are necessary, with each iteration involving changing the design and tracing different signals.